1. Field of the Invention
The present invention relates to technique of providing semiconductor integrated circuit devices with interconnections, and more particularly, to routing of interconnections technique in which noise of clock signals occurring on a clock signal line is reduced.
2. Description of the Background Art
FIG. 12 is a flow chart showing one example of a design flow for semiconductor integrated circuit devices. Generally, in the semi-custom methods using gate arrays and the like, designing methods are standardize and designing procedures are mostly performed automatically with computers. For gate arrays, for example, substrates having basic cells such as transistors regularly arranged (master chips) are produced in advanced and interconnecting procedures only are performed with CAD (Computer Aided Design) or the like by freely laying out patterns of interconnection layers for customizing in a short period of time.
FIG. 13 shows one example of a CAD systems used for the design flow described above. This system was developed for SOG (Sea of Gates) applications. In FIG. 13, T1-T11 denote various kinds of tools, respectively. Simulation, verification, conversion of data, layout and the like are automatically accomplished by those tools on the basis of data in the integrated data base.
First, information such as logic connections based on logic circuit diagrams and timing charts provided by a user (Step S1) is inputted as design data into the data base of the CAD system with logic input tools T1 and T2 (Step S2).
Next, logic verification is performed with the logic simulation tool T4 and the like using a test pattern generated from the timing charts and the like in order to verify the correctness of the logic circuits presented by the user (Step S3). If it does not operate normally (NG), the design is modified. If normal operation is confirmed, timing verification is further performed with the timing verification tool T5 using virtual interconnection lengths (Step S4). When the timing verification is completed, the processing proceeds to the step of placing and interconnecting cells on a selected master chip. The placing and interconnecting are automatically accomplished by the layout tool T11 with libraries of various kinds of cells entered in the design data base DB1 (Step S5). In the case of gate arrays, connections may not be completely made by the automatic placement and routing if the utilization ratio of gates of the master chip is high because the chip size is defined. Accordingly, routing programs and art work data may be modified by hand with the conversational art work editor. When the automatic placement and routing is finished, the interconnection lengths are precisely determined (Step S6), and timing verification is implemented using the same (Step S7). If an error occurs in the results of the final verification of operational timing, the logic circuit or the timing chart may be modified. Next, if normal operation is confirmed in the timing verification, it is converted into an actual pattern, and a mask for forming interconnections is made using the same (Step S8). The test pattern generated from the timing charts presented by the user is used for the logic and the timing verifications, and is also converted into the format for a tester for testing semiconductor integrated circuit devices using the test generation tool T6 and the like (Step S9). Wafers completed via the interconnection forming process with the masks are tested with the test pattern, and the procedure proceeds toward final products. In FIG. 12, the dotted lines represent the CAD system and relations of use of the CAD system.
Next, the automatic placement and routing will be described in detail referring to FIGS. 14-24. FIG. 14 is a plan view showing one example of structure of a master chip selected after the timing verification (Step S4), shown in FIG. 12, is finished. In the figure, reference numeral 50 designates a master chip of a gate array LSI, 52 denotes I/O buffer regions in the periphery of the LSI used to input/output signals, 53 denotes an internal gate region in which internal gates are arranged, 54 denotes predriver cells including predrivers for outputting clock signals provided around the internal gate region 53, and 55 denotes maindriver cells including maindrivers for outputting and distributing clock signals to the internal gate region 53 provided around the internal gate region 53. The internal gate region 53 can be divided into a plurality of unit areas, and one of the unit areas is shown in FIG. 15. FIG. 15 is an enlarged plan view of a unit region Ar2. In the figure, reference numeral 2 designates gate electrodes of PMOS transistors, 2a denotes an N.sup.+ diffusion layer forming a series of PMOS transistors, 3 denotes gate electrodes of NMOS transistors, and 3a denotes a P.sup.+ diffusion layer forming a series of NMOS transistors. The arrow in the upper left side of the figure indicates one unit of basic cell.
Next, FIGS. 16 and 17 show slice cells for realizing supply of two-phase clock signals to the internal gate region 53. FIG. 16 shows a cell used for forming a clock ring for supplying first clock signals CLKA, and FIG. 17 shows a cell used for forming a clock ring for supplying second clock signals CLKB. In FIG. 16, 60 denotes a slice cell including a clock ring, 62 denotes a predriver input line for providing clock signals CLKA applied from outside to inputs of predrivers, 63 denotes a predriver output line for providing outputs of the predrivers to input terminals of maindrivers, and 64a and 64b denote maindriver output lines for providing outputs of the maindrivers to the clock ring. The layout of these interconnections enables selection as to how many predrivers and maindrivers are to be assigned to supply first clock signals CLKA. 61a-61c and 65a, 65b denote Al lines forming the clock ring. 61a-61c represent second layer Al interconnections and 65a, 65b represent first layer Al interconnections, respectively. Structures of clock rings are not limited to this structure. For example, four or more second layer Al lines may be provided, although three second layer Al lines are included in this slice cell. That is, slice cells can be prepared according to different applications. In the same way, in FIG. 17, reference numeral 70 designates a slice cell including a clock ring for supplying second clock signals CLKB, 72 denotes a predriver input line for providing clock signals CLKB which are applied from outside to inputs of predrivers, 73 denotes a predriver output line for providing outputs of the predrivers to input terminals of maindrivers, and 74a and 74b denote maindriver output lines for providing outputs of the maindrivers to the clock ring. In this structure, outputs of three predrivers are commonly applied to inputs of three maindrivers.
FIG. 18 shows the master chip shown in FIG. 14 and the slice cells shown in FIGS. 16 and 17 placed thereon. As can be seen from FIG. 18, since the clock ring for supplying first clock signals CLKA shown in FIG. 16 and the clock ring for supplying second clock signals CLKB shown in FIG. 17 are different in size, clock signal lines are not formed in the same interconnection layer overlapping with each other. The clock rings are placed in the circumferential area of the internal gate region 53, and the clock signal lines 61a and 71a are also placed in the center area thereof. This structure can suppress occurrence of clock skew. Further, interconnections can easily be made so that two-phase clock signals can be effectively supplied to the internal gate region 53 from the circumference thereof.
Subsequently, basic macro-cells are placed and interconnected to realize desired functions. In order to simplify the explanation, description will be given here on relations between the second clock signals CLKB and the macro-cells. FIG. 19 shows a master chip including V.sub.DD power-supply lines 76a-78a and GND power-supply lines 76b-78b, with the slice cell shown in FIG. 17 placed thereon. FIG. 20 shows a basic macro-cell. In FIG. 20, reference numeral 4 designates a V.sub.DD power-supply line for supplying a potential V.sub.DD, and 5 denotes a GND power-supply line for supplying a potential GND. The V.sub.DD power-supply line 4 is provided in one end area of the cell in parallel with the series of gate electrodes 2 of the PMOS transistors arranged in a line and the GND power-supply line 5 is provided in the other end area of the cell in parallel with the series of gate electrodes 3 of the NMOS transistors arranged in a line.
FIG. 21 shows the master chip shown in FIG. 19 and the basic macro-cells shown in FIG. 20 or the basic macro-cells with interconnections provided therein which are placed on the master chip.
After routings of the clock ring and clock driver cells such as predriver cells and maindriver cells and the like are determined, positionings in internal cell rows, i.e., in which rows in the internal gate region 53 the macro-cells are to be placed, are determined. For example, in the semiconductor integrated circuit device shown in FIG. 21, the macro-cells are placed in the second row, the fifth row and the eighth row. The macro-cells can be classified into sequential circuits 35a which require supply of the second clock signals CLKB and combinational circuits 36a which do not require-supply of clock signals. With the macro-cells placed therein, the V.sub.DD power-supply lines 4 and the GND power-supply lines 5 are not connected in areas where no macro-cells exist in the internal cell rows, and the V.sub.DD power-supply lines 4 and the GND power-supply lines 5 are connected in areas where the macro-cells are connected in a row. After placements of macro-cells in the internal cell rows are accomplished, macro-cells having only power-supply lines 4 and 5 are placed on individual internal cell rows to connect the power supply-lines 4 and 5 in the internal cell rows in which internal cells are placed from the left end to the right end of the internal gate region 53. FIG. 22 shows such macro-cells placed therein. An area Ar3 in FIG. 22 has no transistor connection and, therefor, does not serve as an active circuit. However, the power-supply lines 4 and 5 exist in that area, and therefor the power-supply lines 4 and 5 in that internal cell row are connected from the power-supply line 78a on the left end to the power-supply line 77a on the right end all the way.
Next, a determination is made as to where signal lines are to be drawn in interconnection spaces in which no macro-cells exist, and first layer Al interconnections are provided to distribute clock signals from the clock ring to respective macro-cells. FIG. 23 shows the master chip having interconnections for the second clock signals CLKB provided therein. In FIG. 23, 6 denotes clock signal lines of first layer Al interconnections, 38 denotes clock signal lines of second layer Al interconnections, and 39 denotes through holes for connecting the second layer Al lines 71a-71c forming the clock ring and the clock lines 6.
Finally, interconnections for normal signals other than clock signal lines are placed, as it is shown in FIG. 24. In FIG. 24, reference numeral 40 designates signal lines. Placements of signal lines 40 are implemented using interconnection areas in the internal gate region 53 other than cell rows having macro-cells therein. In areas Ar4 and Ar5 in the internal gate region 53, for example, the signal line 40 and the clock signal line 6 are placed in parallel in a considerably long distance.
Conventional semiconductor integrated circuit devices are structured as described above. In such structures, for example, cross-talk may occur between the signal line 40 and the clock signal line 6 in the areas Ar4 and Ar5 due to capacitance between interconnections. In recent years, as structures of semiconductor integrated circuit devices are becoming finer and finer, the problems caused by cross-talk between interconnections are increasing. If a normal signal is mixed into a clock signal CLKB propagating on the clock signal line 6, it causes noise. On the other hand, if a clock signal CLKB propagating on the clock signal line 6 is mixed into a normal signal propagating on the signal line 40, it serves as noise. For overcoming this problem, it is essential to lay out wiring so that the clock signal line 6 and the signal line 40 do not run in parallel to each other. With automatic placement and routing using the CAD system, however, it is difficult to lay out wiring so that clock signal lines and normal signal lines do not run in parallel with conventional routing tools. Accordingly, modifications by hand are required only in areas in which cross-talk is likely to happen in order to reduce such noises, resulting in time-consuming work for design. Thus, there has been a problem that the advantage of gate arrays, i.e., design can be accomplished in a short period of time, could not be fully put into practice.